Field
Embodiments described herein relate to semiconductor packaging. More particularly embodiments relate to fan-out wafer level packages and methods of fabrication.
Background Information
Packaging technologies for integrated circuits such as embedded wafer level ball grid array generally involve encapsulating an integrated circuit (IC) die in encapsulation material and then building wafer redistribution layer. The molding compound creates a fanout area that creates more space for a higher I/O count.
Pressures from advances in packaging technologies are leading to IC die with higher I/O count. In addition, the shrinking sizes of electronic devices and performance requirement are creating challenges for IC die packaging that has resulted in package on package (PoP) applications. There is an increased need for PoP applications that result in packages with higher I/O counts and smaller sizes for use in size-sensitive applications.